DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1063

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.2
Multi mode should be selected when performing A/D conversion once on one or more channels.
In multi mode, A/D conversion is performed once for a maximum of eight specified analog input
channels, as follows:
1. A/D conversion starts from the analog input channel with the lowest number (e.g. AN0, AN1,
2. When A/D conversion is completed on each channel, the A/D conversion result is sequentially
3. After A/D conversion on all selected channels has completed, the ADF bit in ADCSR is set to
4. The ADST bit that remains 1 during A/D conversion is automatically cleared to 0 when A/D
A/D conversion is to be performed once on all the specified channels. The conversion results are
transferred for storage into the A/D data registers corresponding to the channels.
When the operating mode or analog input channel selection must be changed during A/D
conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion.
After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from
the first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels (AN0 to AN2) are selected in multi mode are described
next. Figure 20.3 shows a timing diagram for this example.
1. Multi mode is selected (MDS2 = 1, MDS1 = 0), analog input channels AN0 to AN2 are
2. A/D conversion of the first channel (AN0) starts. When A/D conversion is completed, the A/D
3. Next, the second channel (AN1) is selected automatically and A/D conversion starts.
4. Conversion proceeds in the same way through the third channel (AN2).
5. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
6. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested.
…, AN3) when the ADST bit in ADCSR is set to 1 by software, MTU2, or external trigger
input.
transferred to the A/D data register corresponding to that channel.
1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated.
conversion is completed, and the A/D converter becomes idle. If the ADST bit is cleared to 0
during A/D conversion, A/D conversion is halted and the A/D converter becomes idle. The
ADF bit is cleared by reading ADF while ADF = 1, then writing 0 to the ADF bit.
selected (CH[2:0] = 010), and A/D conversion is started (ADST = 1).
conversion result is transferred into ADDRA.
and the ADST bit cleared to 0.
Multi Mode
Rev. 3.00 Sep. 28, 2009 Page 1031 of 1650
Section 20 A/D Converter (ADC)
REJ09B0313-0300