DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 195

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.9
IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow
exception. IBNR also indicates the bank number to which saving is performed next through the
bits BN3 to BN0.
Initial value:
Bit
15, 14
13
12 to 4
R/W:
Bit:
Bank Number Register (IBNR)
R/W
Bit Name
BE[1:0]
BOVE
⎯
15
0
BE[1:0]
R/W
14
0
BOVE
R/W
13
0
Initial
Value
All 0
00
0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
R
10
R
0
-
Description
Register Bank Enable
These bits enable or disable use of register banks.
00: Use of register banks is disabled for all interrupts.
01: Use of register banks is enabled for all interrupts
10: Reserved (setting prohibited)
11: Use of register banks is controlled by the setting of
Register Bank Overflow Enable
Enables of disables register bank overflow exception.
0: Generation of register bank overflow exception is
1: Generation of register bank overflow exception is
Reserved
These bits are always read as 0. The write value should
always be 0.
R
9
0
disabled
enabled
-
The setting of IBCR is ignored.
except NMI and user break. The setting of IBCR is
ignored.
IBCR.
R
8
0
-
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 163 of 1650
R
6
0
-
Section 6 Interrupt Controller (INTC)
R
5
0
-
R
4
0
-
R
3
0
REJ09B0313-0300
R
2
0
BN[3:0]
R
1
0
R
0
0