DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 983

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(4)
The interrupt register (IRR) is a 16-bit read/write-clearable register containing status flags for the
various interrupt sources.
• IRR (Address = H'008)
Bit 15 — Timer Compare Match Interrupt 1 (IRR15): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 1 (TCMR1). When the value set in the
TCMR1 matches to Cycle Time (TCMR1 = CYCTR), this bit is set.
Bit 14 — Timer Compare Match Interrupt 0 (IRR14): Indicates that a Compare-Match
condition occurred to the Timer Compare Match Register 0 (TCMR0). When the value set in the
TCMR0 matches to Local Time (TCMR0 = TCNTR), this bit is set.
Bit 13 - Timer Overrun Interrupt/Next_is_Gap Reception Interrupt/Message Error
Interrupt (IRR13): This interrupt assumes a different meaning depending on the RCAN-TL1
mode. It indicates that:
Bit 15: IRR15
0
1
Bit 14: IRR14
0
1
Initial value:
⎯ The Timer (TCNTR) has overrun when RCAN-TL1 is working in event-trigger mode
Interrupt Request Register (IRR)
R/W:
(including test modes)
Bit:
IRR15 IRR14 IRR13 IRR12 IRR11 IRR10
R/W
15
0
R/W
14
0
Description
Timer Compare Match has not occurred to the TCMR1 (Initial value)
[Clearing condition] Writing 1
Timer Compare Match has occurred to the TCMR1
[Setting condition] TCMR1 matches to Cycle Time (TCMR1 = CYCTR)
Description
Timer Compare Match has not occurred to the TCMR0 (Initial value)
[Clearing condition] Writing 1
Timer Compare Match has occurred to the TCMR0
[Setting condition] TCMR0 matches to the Timer value (TCMR0 = TCNTR)
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
IRR9
R
9
0
IRR8
R
8
0
Section 19 Controller Area Network (RCAN-TL1)
R/W
IRR7
7
0
Rev. 3.00 Sep. 28, 2009 Page 951 of 1650
IRR6
R/W
6
0
IRR5
R/W
5
0
R/W
IRR4
4
0
R/W
IRR3
3
0
IRR2
REJ09B0313-0300
R
2
0
IRR1
R
1
0
R/W
IRR0
0
1