DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1477

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This section gives information on the on-chip I/O registers of this LSI in the following structures.
1. Register Addresses (by functional module, in order of the corresponding section numbers)
2. Register Bits
3. Register States in Each Operating Mode
4. Notes when Writing to the On-Chip Peripheral Modules
⎯ Registers are described by functional module, in order of the corresponding section
⎯ Access to reserved addresses which are not described in this register address list is
⎯ When registers consist of 16 or 32 bits, the addresses of the MSBs are given when big
⎯ Bit configurations of the registers are described in the same order as the Register Addresses
⎯ Reserved bits are indicated by — in the bit name.
⎯ No entry in the bit-name column indicates that the whole register is allocated as a counter
⎯ Register states are described in the same order as the Register Addresses (by functional
⎯ For the initial state of each bit, refer to the description of the register in the corresponding
⎯ The register states described are for the basic operating modes. If there is a specific reset
⎯ To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
numbers.
prohibited.
endian mode is selected.
(by functional module, in order of the corresponding section numbers).
or for holding data.
module, in order of the corresponding section numbers).
section.
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
required. Care must be taken in system design. When the CPU writes data to the internal
peripheral registers, the CPU performs the succeeding instructions without waiting for the
completion of writing to registers. For example, a case is described here in which the
system is transferring to the software standby mode for power savings. To make this
transition, the SLEEP instruction must be performed after setting the STBY bit in the
STBCR register to 1. However a dummy read of the STBCR register is required before
executing the SLEEP instruction. If a dummy read is omitted, the CPU executes the SLEEP
instruction before the STBY bit is set to 1, thus the system enters sleep mode not software
standby mode. A dummy read of the STBCR register is indispensable to complete writing
to the STBY bit. To reflect the change by internal peripheral registers while performing the
succeeding instructions, execute a dummy read of registers to which write instruction is
given and then perform the succeeding instructions.
Section 30 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 1445 of 1650
Section 30 List of Registers
REJ09B0313-0300