DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 524

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.6
The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring
data from the buffer register to the timer general register in PWM mode. The MTU2 has three
TBTM registers, one each for channels 0, 3, and 4.
Rev. 3.00 Sep. 28, 2009 Page 492 of 1650
REJ09B0313-0300
Bit
7 to 3
2
1
0
Bit Name
—
TTSE
TTSB
TTSA
Timer Buffer Operation Transfer Mode Register (TBTM)
Initial value:
Initial
Value
All 0
0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timing Select E
Specifies the timing for transferring data from TGRF_0
to TGRE_0 when they are used together for buffer
operation.
In channels 3 and 4, bit 2 is reserved. It is always read
as 0 and the write value should always be 0.
0: When compare match E occurs in channel 0
1: When TCNT_0 is cleared
Timing Select B
Specifies the timing for transferring data from TGRD to
TGRB in each channel when they are used together for
buffer operation.
0: When compare match B occurs in each channel
1: When TCNT is cleared in each channel
Timing Select A
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
R
5
0
-
R
4
0
-
R
3
0
-
TTSE
R/W
2
0
TTSB
R/W
1
0
TTSA
R/W
0
0