DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 810

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 Serial Communication Interface with FIFO (SCIF)
(1)
The data length is fixed at eight bits. No parity bit can be added.
(2)
An internal clock generated by the on-chip baud rate generator by the setting of the C/A bit in
SCSMR and CKE[1:0] in SCSCR, or an external clock input from the SCK pin can be selected as
the SCIF transmit/receive clock.
When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight
clock pulses are output per transmitted or received character. When the SCIF is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs
while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive
FIFO data trigger number.
(3)
• SCIF Initialization (Clock Synchronous Mode)
Rev. 3.00 Sep. 28, 2009 Page 778 of 1650
REJ09B0313-0300
Before transmitting, receiving, or changing the mode or communication format, the software
must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the
SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0,
however, does not initialize the RDF, PER, FER, and ORER flags and receive data register
(SCRDR), which retain their previous contents.
Transmit/Receive Formats
Clock
Transmitting and Receiving Data