DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 861

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: Hatching boxes represent SSU internal operations.
[3]
[1]
[2]
No
Figure 16.17 Flowchart Example of Simultaneous Transmission/Reception
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Clear bits TE and RE in SSER to 0
Clear the TEND bit in SSSR to 0
Read the TEND bit in SSSR
Write transmit data to SSTDR
Read receive data in SSRDR
Read the TDRE bit in SSSR.
RDRF automatically cleared
TDRE automatically cleared
End transmission/reception
One bit period elapsed?
transmission/reception?
Consecutive data
Initial setting
ORER = 1?
Read SSSR
TEND = 1?
Yes
TDRE = 1?
RDRF = 1?
Start
Yes
Yes
Yes
No
No
(Clock Synchronous Communication Mode)
No
Yes
No
No
Yes
Error processing
[5]
[4]
Section 16 Synchronous Serial Communication Unit (SSU)
[1] Initial setting:
[2] Check the SSU state and write transmit data:
[3] Check the SSU state:
[4] Receive error processing:
[5] Procedure for consecutive data transmission/reception:
Specify the transmit/receive data format.
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by SSRXI interrupt.
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Rev. 3.00 Sep. 28, 2009 Page 829 of 1650
REJ09B0313-0300