DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 387

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

• Setting for Area 3

Mode register setting timing is shown in figure 9.32. A PALL command (all bank pre-charge

command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An

MRS command (mode register write command) is finally issued. Idle cycles, of which number is

specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the

first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,

are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which

number is one or more, are inserted between the MRS and a command to be issued next.

It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after

power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse

width of the reset signal is longer than the idle time, mode register setting can be started

immediately after the reset, but care should be taken when the pulse width of the reset signal is

shorter than the idle time.

Data Bus Width

Data Bus Width

Burst read/single write (burst length 1):

Burst read/burst write (burst length 1):

Access Address

Access Address

Rev. 3.00 Sep. 28, 2009 Page 355 of 1650

Section 9 Bus State Controller (BSC)

External Address Pin

External Address Pin

REJ09B0313-0300