DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1137

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
23.3.2
SYSSTS is a register that monitors the line status (D+ and D− lines) of the USB data bus.
This register is initialized by a power-on reset, a software reset, or a USB bus reset.
Initial value:
Bit
15 to 11 ⎯
10
9 to 6
5
4 to 2
R/W:
Bit:
System Configuration Status Register (SYSSTS)
Bit Name
SOFEN
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
1
All 0
0
All 0
12
R
0
-
11
R
0
-
R/W
R
R
R
R
R
10
R
1
-
R
9
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
The read value is undefined. This bit cannot be
modified.
Reserved
These bits are always read as 0. The write value
should always be 0.
SOF Issuance Enable
Indicates whether SOF issuance by this module
internal circuit is enabled or disabled, after the UACT
bit in DVSTCTR is written to by software in host
mode operation.
0: SOF issuance to the USB port is disabled.
1: SOF issuance to the USB port is enabled.
Reserved
These bits are always read as 0. The write value
should always be 0.
R
8
0
-
Section 23 USB 2.0 Host/Function Module (USB)
R
7
0
-
Rev. 3.00 Sep. 28, 2009 Page 1105 of 1650
R
6
0
-
SOFEN
R
5
0
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
LNST[1:0]
*
R
0
*

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