DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1012

Manufacturer Part Number

DS72030W200FPV

MPU, 32BIT, SH7203, ROMLESS, 240QFP

Manufacturer

Renesas Electronics America

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

1.1V To 1.3V

Operating Temperature Range

-20Â°C To +85Â°C

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-TL1)

This register is a 16-bit read-only register, and allows the CPU to monitor the Timer Compare

Match status and the Timer Overrun Status.

• TSR (Address = H'088)

Bits 15 to 5: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.

Bits 4 to 0 — RCAN-TL1 Timer Status (TSR[4:0]): This read-only field allows the CPU to

monitor the status of the Cycle Counter, the Timer and the Compare Match registers. Writing to

this field has no effect.

Bit 4 — Start of New System Matrix (TSR4): Indicates that a new system matrix is starting.

When CCR = 0, this bit is set at the successful completion of reception/transmission of time

reference message.

Bit 3 — Timer Compare Match Flag 2 (TSR3): Indicates that a Compare-Match condition

occurred to the Timer Compare Match Register 2 (TCMR2). When the value set in the TCMR2

matches to Cycle Time Register (TCMR2 = CYCTR), this bit is set if TTCR0 bit12 = 1. Please

note that this bit is read-only and is cleared when IRR11 (Timer Compare Match Interrupt 2) is

Rev. 3.00 Sep. 28, 2009 Page 980 of 1650

REJ09B0313-0300

Initial value:

Timer Status Register (TSR)

A new system matrix is not starting (initial value)

[Clearing condition] Writing ‘1’ to IRR10 (Cycle Counter Overflow Interrupt)

Cycle counter reached zero

[Setting condition]

When the Cycle Counter value changes from the maximum value (CMAX) to

H'0. Reception/transmission of time reference message is successfully

completed when CMAX!= 3'b111 and CCR = 0