DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1494

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 30 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 1462 of 1650
REJ09B0313-0300
Module
Name
RCAN-
TL1
Register Name
Cycle Time Register_1
Reference Mark Register_1
Timer Compare Match Register 0_1 TCMR0_1
Timer Compare Match Register 1_1 TCMR1_1
Timer Compare Match Register 2_1 TCMR2_1
Tx-Trigger Time Selection
Register_1
Mailbox n Control 0_H_1
(n = 0 to 31)
Mailbox n Control 0_L_1
(n = 0 to 31)
Mailbox n Local Acceptance Filter
Mask 0_1 (n = 0 to 31)
Mailbox n Local Acceptance Filter
Mask 1_1 (n = 0 to 31)
Mailbox n Data 01_1 (n = 0 to 31)
Mailbox n Data 23_1 (n = 0 to 31)
Mailbox n Data 45_1 (n = 0 to 31)
Mailbox n Data 67_1 (n = 0 to 31)
Mailbox n Control 1_1 (n = 0 to 31)
Mailbox n Time Stamp_1
(n = 0 to 15, 30, 31)
Mailbox n Trigger Time_1
(n = 24 to 30)
Mailbox n TT Control_1
(n = 24 to 29)
Abbreviation
CYCTR_1
RFMK_1
TTTSEL_1
MBn_CONTROL0_H_1
(n = 0 to 31)
MBn_CONTROL0_L_1
(n = 0 to 31)
MBn_LAFM0_1
(n = 0 to 31)
MBn_LAFM1_1
(n = 0 to 31)
MBn_DATA_01_1
(n = 0 to 31)
MBn_DATA_23_1
(n = 0 to 31)
MBn_DATA_45_1
(n = 0 to 31)
MBn_DATA_67_1
(n = 0 to 31)
MBn_CONTROL1_1
(n = 0 to 31)
MBn_TIMESTAMP_1
(n = 0 to 15, 30, 31)
MBn_TTT_1
(n = 24 to 30)
MBn_TTCONTROL_1
(n = 24 to 29)
Number
of Bits
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Address
H'FFFF0890
H'FFFF0894
H'FFFF0898
H'FFFF089C
H'FFFF08A0
H'FFFF08A4
H'FFFF0900
H'FFFF0902
H'FFFF0904
H'FFFF0906
H'FFFF0908
H'FFFF090A
H'FFFF090C
H'FFFF090E
H'FFFF0910
H'FFFF0912
H'FFFF0914
H'FFFF0916
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
Access
Size
16
16
16
16
16
16
16, 32
16
16, 32
16
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16
16
16
16