DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1620

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 31 Electrical Characteristics
31.4.14 FLCTL Timing
Table 31.19 AND Type Flash Memory Interface Timing
Conditions: V
Rev. 3.00 Sep. 28, 2009 Page 1588 of 1650
REJ09B0313-0300
Item
Command issue setup time
Command issue hold time
Data output setup time
Data output hold time
Data output setup time 2
Data output hold time 2
FWE cycle time
FWE low pulse width
FWE high pulse width
Command to address transition time
Address to data read transition time
Address to ready/busy transition time
Ready/busy to data read transition
time
Data read setup time
FSC cycle time
FSC high pulse width
FSC low pulse width
Read data setup time
Read data hold time
Status read data setup time
Address to data write transition time
AV
V
USBAPV
CC
SS
CC
= PLLV
= PLLV
= 3.0 to 3.6 V, USBAV
SS
= 0V, T
SS
CC
= PV
= USBDV
SS
a
= −20 to 85 °C
= AV
CC
Symbol Min.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SS
= 1.1 to 1.3 V, PV
ACDS
ACDH
ADOS
ADOH
ADOS2
ADOH2
ACWC
AWP
AWPH
ACAS
AADDR
AADRB
ARBDR
ADRS
ASCC
ASP
ASPL
ARDS
ARDH
ASRDS
AADDW
= USBDV
CC
= 1.1 to 1.3 V, USBAPV
2 × t
2 × t
t
t
0.5 × t
0.5 × t
2 × t
t
t
4 × t
32 × t
⎯
3 × t
t
t
0.5 × t
0.5 × t
24
5
2 × t
4 × t
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
SS
− 10
− 10
− 5
− 5
− 10
− 5
= USBAV
fcyc
fcyc
fcyc
fcyc
fcyc
fcyc
pcyc
pcyc
fcyc
fcyc
fcyc
fcyc
− 10
− 10
− 5
+ 24
CC
− 10
− 10
− 5
− 5
= USBDPV
SS
= USBDPV
Max.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
35 × t
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
CC
= 3.0 to 3.6 V,
CC
pcyc
= 3.0 to 3.6 V,
Unit Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS
=
Figures 31.64,
31.68
Figures 31.64,
31.65, 31.68
Figure 31.67
Figure 31.65
Figures 31.64,
31.65, 31.68
Figure 31.65
Figure 31.66
Figure 31.66
Figures 31.66,
31.67
Figures 31.66,
31.68
Figure 31.68
Figure 31.67