DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1652

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 3.00 Sep. 28, 2009 Page 1620 of 1650
REJ09B0313-0300
Item
5.6.5 Integer Division
Exceptions
5.9.4 Note before
Exception Handling
Begins Running
8.4.4 Notes
9.5.13 Bus Arbitration
Figure 9.55 Bus
Arbitration Timing
9.6 Usage Notes
10.3.4 DMA Channel
Control Registers
(CHCR)
Page
141
147
238
389
391
405
Revision (See Manual for Details)
Description amended
1. The exception service routine start address which
Newly added
Description amended
1. Programs that access memory-mapped cache of the
Figure title amended
Newly added
Table amended
Bit
19
corresponds to the integer division
occurred is fetched from the exception handling vector
table.
operand cache should be placed in a cache-disabled
space. Programs that access memory-mapped cache of
the instruction cache should be placed in a cache-disabled
space, and in each of the beginning and the end of that,
two or more read accesses to on-chip peripheral modules
or external address space (cache-disabled address)
should be executed.
Bit Name
HE
Initial
Value
0
R/W
R/(W)*
1
Description
Half-End Flag
This bit is set to 1 when the transfer count reaches half
of the DMATCR value that was specified before
transfer starts.
If DMA transfer ends because of an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR before the transfer count reaches
half of the initial DMATCR value, the HE bit is not set
to 1. If DMA transfer ends due to an NMI interrupt, a
DMA address error, or clearing of the DE bit or the
DME bit in DMAOR after the HE bit is set to 1, the bit
remains set to 1.
To clear the HE bit, write 0 to it after HE = 1 is read.*
0: DMATCR > (DMATCR set before transfer starts)/2
[Clearing condition]
•
1: DMATCR ≤ (DMATCR set before transfer starts)/2
during DMA transfer or after DMA transfer is
terminated
Writing 0 after reading HE = 1.*
exception that
2
2