DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 36

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 4 of 1650
REJ09B0313-0300
Items
Bus state controller
(BSC)
Direct memory access
controller (DMAC)
Clock pulse generator
(CPG)
Watchdog timer
(WDT)
Specification
Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
The following features settable for each area independently
⎯ Bus size (8, 16, or 32 bits): Available sizes depend on the area.
⎯ Number of access wait cycles (different wait cycles can be
⎯ Idle wait cycle insertion (between same area access cycles or
⎯ Specifying the memory to be connected to each area enables
⎯ PCMCIA interface
⎯ Outputs a chip select signal (CS0 to CS7) according to the target
SDRAM refresh
Auto refresh or self refresh mode selectable
SDRAM burst access
Eight channels; external request available for four of them
Can be activated by on-chip peripheral modules
Burst mode and cycle steal mode
Intermittent mode available (16 and 64 cycles supported)
Transfer information can be automatically reloaded
Clock mode: Input clock can be selected from external input (EXTAL,
CKIO, or USB_X1) or crystal resonator
Input clock can be multiplied by 16 (max.) by the internal PLL circuit
Three types of clocks generated:
⎯ CPU clock: Maximum 200 MHz
⎯ Bus clock: Maximum 66 MHz
⎯ Peripheral clock: Maximum 33 MHz
On-chip one-channel watchdog timer
A counter overflow can reset the LSI
specified for read and write access cycles in some areas)
different area access cycles)
direct connection to SRAM, SRAM with byte selection, SDRAM,
and burst ROM (clocked synchronous or asynchronous). The
address/data multiplexed I/O (MPX) interface and burst MPX-I/O
interface are also available.
area (CS assert or negate timing can be selected by software)

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