DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 944
DS72030W200FPV
Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet
1.R5S72030W200FP.pdf
(1686 pages)
Specifications of DS72030W200FPV
Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section 18 Serial Sound Interface (SSI)
18.5
18.5.1
If an underflow or overflow occurs while the DMA is in operation, the module should be restarted.
The transmit and receive buffers in the SSI consists of 32-bit registers that share the L and R
channels. Therefore, data to be transmitted and received at the L channel may sometimes be
transmitted and received at the R channel if an underflow or overflow occurs, for example, under
the following condition: the control register (SSICR) has a 32-bit setting for both data word length
(DWL2 to DWL0) and system word length (SWL2 to SWL0).
If an error occurrence is confirmed with two types of error interrupts (underflow, overflow) or the
corresponding error status flag (the bits UIRQ, OIRQ in SSISR), write 0 to the EN and DMEN bit
in SSICR to disable DMA transfer requests in this module, thus stopping the operation. (In this
case, the direct memory access controller setting should also be stopped.) After this, write 0 to the
error status flag bit to clear the error status, set the direct memory access controller again and
restart the transfer.
Rev. 3.00 Sep. 28, 2009 Page 912 of 1650
REJ09B0313-0300
Usage Notes
Limitations from Underflow or Overflow during DMA Operation
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