DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1300

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 24 LCD Controller (LCDC)
24.3.22 LCDC Memory Access Interval Number Register (LDLIRNR)
LDLIRNR controls the bus clock interval when the LCDC reads VRAM. As the LCDC does not
access VRAM during the bus clock period specified by LDLIRNR, external bus accesses by the
CPU or the DMAC is possible during that period.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 1268 of 1650
REJ09B0313-0300
Bit
15 to 8
7 to 0
Bus cycle
R/W:
CKIO
Bit:
15
R
0
-
Bit Name
⎯
LIRN7 to
LIRN0
LCDC1 LCDC2
(When displaying routated image,
4/8/16/32 can be selected.)
14
R
0
-
16 bursts
13
R
0
-
LCDC3
Initial
Value
All 0
All 0
12
R
0
-
...
LCDC16
11
R
0
-
R/W
R
R/W
10
R
0
-
The number of bus clocks other than LCDC is set to
CPU
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
VRAM Read Bus Clock Interval
These bits specify the number of the bus clocks that are
inserted during burst bus cycles to read VRAM by the
LCDC.
H'00: One bus clock
H'01: Two bus clocks
H'FF: 256 bus clocks
R
9
0
-
LIRN7 to LIRN0. (1 to 256 bus clocks)
R
8
0
-
CPU
:
LIRN7 LIRN6 LIRN5 LIRN4 LIRN3 LIRN2 LIRN1 LIRN0
R/W
7
0
R/W
6
0
...
R/W
5
0
R/W
CPU
4
0
R/W
3
0
LCDC1
R/W
2
0
R/W
1
0
...
R/W
0
0