DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 29

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.3 Switching Pin Function of Port A .................................................................................... 1363
25.4 Usage Notes ..................................................................................................................... 1364
Section 26 I/O Ports .........................................................................................1365
26.1 Features............................................................................................................................ 1365
26.2 Port A............................................................................................................................... 1366
26.3 Port B ............................................................................................................................... 1368
26.4 Port C ............................................................................................................................... 1372
26.5 Port D............................................................................................................................... 1376
26.6 Port E ............................................................................................................................... 1380
26.7 Port F................................................................................................................................ 1384
26.8 Usage Notes ..................................................................................................................... 1391
Section 27 On-Chip RAM ...............................................................................1393
27.1 Features............................................................................................................................ 1393
27.2 Usage Notes ..................................................................................................................... 1395
25.2.10 Port F Control Registers H1 to H4, L1 to L4
25.2.11 IRQOUT Function Control Register (IFCR) .................................................... 1360
25.2.12 SSI Oversampling Clock Selection Register (SCSR) ....................................... 1361
26.2.1 Register Descriptions .......................................................................................... 1366
26.2.2 Port A Data Register L (PADRL) ....................................................................... 1366
26.3.1 Register Descriptions .......................................................................................... 1368
26.3.2 Port B Data Register L (PBDRL) ....................................................................... 1369
26.3.3 Port B Port Register L (PBPRL) ......................................................................... 1371
26.4.1 Register Descriptions .......................................................................................... 1372
26.4.2 Port C Data Register L (PCDRL) ....................................................................... 1373
26.4.3 Port C Port Register L (PCPRL) ......................................................................... 1375
26.5.1 Register Descriptions .......................................................................................... 1376
26.5.2 Port D Data Registers L (PDDRL) ..................................................................... 1377
26.5.3 Port D Port Registers L (PDPRL) ....................................................................... 1379
26.6.1 Register Descriptions .......................................................................................... 1380
26.6.2 Port E Data Registers L (PEDRL) ...................................................................... 1381
26.6.3 Port E Port Registers L (PEPRL)........................................................................ 1383
26.7.1 Register Descriptions .......................................................................................... 1385
26.7.2 Port F Data Registers H and L (PFDRH, PFDRL) ............................................. 1385
26.7.3 Port F Port Registers H and L (PFPRH, PFPRL)................................................ 1389
27.2.1 Page Conflict....................................................................................................... 1395
27.2.2 RAME and RAMWE Bits .................................................................................. 1395
27.2.3 Areas where Placing Instructions Is Prohibited .................................................. 1396
(PFCRH1 to PFCRH4, PFCRL1 to PFCRL4) .................................................. 1346
Rev. 3.00 Sep. 28, 2009 Page xxvii of xxx
REJ09B0313-0300