DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 147

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4.5
Bit
7 to 5
4
3
2 to 0
Setting
00
01
10
11
Bit Name
⎯
IFC
⎯
PFC[2:0]
Output
Output
Output
Output off (Hi-Z)
Normal
Operation
CKOEN[1:0] Settings
Initial
Value
All 0
0
0
011
Release of Bus
Mastership
Output off (Hi-Z)
Output
Output
Output off (Hi-Z)
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Internal Clock Frequency Division Ratio
This bit specifies the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit.
0: × 1 time
1: × 1/2 time
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit.
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
Peripheral Clock Frequency Division Ratio
Software Standby
Mode
Output off (Hi-Z)
Low-level output
Output (unstable
clock output)
Output off (Hi-Z)
Rev. 3.00 Sep. 28, 2009 Page 115 of 1650
Section 4 Clock Pulse Generator (CPG)
Deep Standby
Mode
Low-level or high-level
output
Low-level or high-level
output
Low-level or high-level
output
Output off (Hi-Z)
REJ09B0313-0300