DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 764

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.6
SCSCR operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write to SCSCR.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 732 of 1650
REJ09B0313-0300
Bit
15 to 8
7
R/W:
Bit:
Serial Control Register (SCSCR)
Bit Name
⎯
TIE
15
R
0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
12
R
0
-
11
R
0
-
R/W
R
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when the serial transmit data
is transferred from the transmit FIFO data register
(SCFTDR) to the transmit shift register (SCTSR), when
the quantity of data in the transmit FIFO register
becomes less than the specified number of
transmission triggers, and when the TDFE flag in the
serial status register (SCFSR) is set to1.
0: Transmit-FIFO-data-empty interrupt request (TXI) is
1: Transmit-FIFO-data-empty interrupt request (TXI) is
Note:
Transmit Interrupt Enable
R
9
0
disabled
enabled*
-
R
8
0
*
-
The TXI interrupt request can be cleared by
writing a greater quantity of transmit data
than the specified transmission trigger
number to SCFTDR and by clearing TDFE
to 0 after reading 1 from TDFE, or can be
cleared by clearing TIE to 0.
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
R/W
REIE
3
0
R
2
0
-
R/W
1
0
CKE[1:0]
R/W
0
0