DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 753

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This LSI has a four-channel serial communication interface with FIFO (SCIF) that supports both
asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for
both transmission and reception independently for each channel that enable this LSI to perform
efficient high-speed continuous communication.
15.1
• Asynchronous serial communication:
• Clock synchronous serial communication:
• Full duplex communication: The transmitting and receiving sections are independent, so the
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
⎯ Serial data communication is performed by start-stop in character units. The SCIF can
⎯ Data length: 7 or 8 bits
⎯ Stop bit length: 1 or 2 bits
⎯ Parity: Even, odd, or none
⎯ Receive error detection: Parity, framing, and overrun errors
⎯ Break detection: Break is detected when a framing error is followed by at least one frame at
⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate
⎯ Data length: 8 bits
⎯ Receive error detection: Overrun errors
SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so
high-speed continuous data transfer is possible in both the transmit and receive directions.
SCK pin (external)
Section 15 Serial Communication Interface with FIFO
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are eight selectable serial data
communication formats.
the space 0 level (low level). It is also detected by reading the RxD level directly from the
serial port register when a framing error occurs.
with other chips having a clock synchronous communication function. There is one serial
data communication format.
Features
(SCIF)
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 721 of 1650
REJ09B0313-0300