DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1125

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
22.4.7
The FLCTL can read the status register of an AND-type or NAND-type flash memory. The data in
the status register of an AND-type or NAND-type flash memory is input through the I/O7 to I/O0
pins and stored in the bits STAT[7:0] in FLBSYCNT. The bits STAT[7:0] in FLBSYCNT can be
read by the CPU. If a program error or erase error is detected when the status register value is
stored in the bits STAT[7:0] in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and
generates an interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled.
(1)
The status register of AND-type flash memory can be read by asserting the output enable signal
OE (OE = 0). If programming is executed in command access mode or sector access mode while
the DOSR bit in FLCMDCR is set to 1, the FLCTL automatically asserts the OE signal and reads
the status register of AND-type flash memory. When the status register of AND-type flash
memory is read, the I/O7 to I/O0 pins indicate the following information as described in table
22.3.
Table 22.3 Status Read of AND-Type Flash Memory
I/O
I/O7
I/O6
I/O5
I/O4
I/O3 to I/O0
Status Read of AND-Type Flash Memory
Status Read
Status (definition)
Reserved
Program check
Reserved
Ready/busy
Erase check
Description
0: Busy state
1: Ready state
0: Pass (erased)
1: Fail (erase failure)
0: Pass (programmed)
1: Fail (program failure)
Section 22 AND/NAND Flash Memory Controller (FLCTL)
Rev. 3.00 Sep. 28, 2009 Page 1093 of 1650
REJ09B0313-0300

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