DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 442

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 10 Direct Memory Access Controller (DMAC)
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
Rev. 3.00 Sep. 28, 2009 Page 410 of 1650
REJ09B0313-0300
Bit
1
0
Bit Name
TE
DE
Initial
Value
0
0
R/W
R/(W)*
R/W
1
Description
Transfer End Flag
This bit is set to 1 when DMATCR becomes 0 and
DMA transfer ends.
The TE bit is not set to 1 in the following cases.
•
•
To clear the TE bit, write 0 after reading TE = 1.*
Even if the DE bit is set to 1 while the TEMASK bit is 0
and this bit is 1, transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
[Clearing condition]
•
1: DMA transfer ends by the specified count
DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits TE,
NMIF in DMAOR, and AE must be 0. In an external
request or peripheral module request, DMA transfer
starts if DMA transfer request is generated by the
devices or peripheral modules after setting the bits DE
and DME to 1. If the DREQ signal is detected by
low/high level in external request mode, or in
peripheral module request mode, the NMIF bit and the
AE bit must be 0 if the TEMASK bit is 1. If the
TEMASK bit is 0, the TE bit must also be 0. If the
DREQ signal is detected by a rising/falling edge in
external request mode, all of the bits TE, NMIF, and
AE must be 0 as in the case of auto request mode.
Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
terminated
(DMATCR = 0)
DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR becomes 0.
DMA transfer is ended by clearing the DE bit and
DME bit in DMA operation register (DMAOR).
Writing 0 after reading TE = 1*
2
2