DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 854

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 16 Synchronous Serial Communication Unit (SSU)
16.4.6
When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is
cleared to 0, the SCS pin functions as an input (Hi-Z) to detect a conflict error. A conflict error
detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after
transfer ends. When a low level signal is input to the SCS pin within the period, a conflict error
occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
Rev. 3.00 Sep. 28, 2009 Page 822 of 1650
REJ09B0313-0300
External input to SCS
Internal-clocked SCS
Internal signal for
Internal signal for
before resuming the transmission or reception.
transfer enable
transfer enable
SCS Pin Control and Conflict Error
SCS output
Figure 16.11 Conflict Error Detection Timing (After Transfer End)
Figure 16.10 Conflict Error Detection Timing (Before Transfer)
MSS
SCS
MSS
CE
Pφ
CE
(Hi-Z)
Transfer
end
detection period
Conflict error
Data written
to SSTDR
internally clocking SCS
(Hi-Z)
Worst time for
Conflict error detection
period