DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1244

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 23 USB 2.0 Host/Function Module (USB)
(b)
Figure 23.16 shows the timing at which, when using a pipe with a double buffer, the other buffer
can be accessed after reading from or writing to one buffer has been completed.
When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns and
6 clock cycles at a peripheral clock after the access made just prior to toggling.
The same timing applies when a short packet is being sent based on the BVAL = 1 setting using
the IN direction pipe.
Rev. 3.00 Sep. 28, 2009 Page 1212 of 1650
REJ09B0313-0300
Figure 23.16 Timing at which the FRDY and DTLN Bits are Determined after Reading
Timing at which the FIFO Port can be Accessed after Reading/Writing has been
Completed when Using a Double Buffer
Figure 23.15 Timing at which the FRDY and DTLN Bits are Determined after
PMS_N
CURPIPE
FRDY
DTLN
PMS_N
CURPIPE
FRDY
DTLN
from or Writing to a Double Buffer has been Completed
Access just prior to buffer toggling
Writing of the CURPIPE bit
Buffer-A
Buffer-A
PIPE-A
PIPE-A
PIPE-A
min. bus clock × 1
min. 20 ns
Changing a Pipe
max. 50 ns +
bus clock × 3
Undefined
max. 300 ns +
bus clock × 6
Undefined
Undefined
PIPE-A
PIPE-B
max. 450 ns +
bus clock × 8
Buffer-B
Buffer-B
PIPE-B
PIPE-B