DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1092

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 22 AND/NAND Flash Memory Controller (FLCTL)
Rev. 3.00 Sep. 28, 2009 Page 1060 of 1650
REJ09B0313-0300
Bit
17
16
15
14
13, 12
Bit Name
QTSEL
—
FCKSEL
—
ECCPOS
[1:0]
Initial
Value
0
0
0
0
00
R/W
R/W
R
R/W
R
R/W
Description
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with FCKSEL.
•
•
•
•
Reserved
This bit is always read as 0. The write value should
always be 0.
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with QTSEL. Refer to
the description of QTSEL.
Reserved
This bit is always read as 0. The write value should
always be 0.
ECC Position Specification 1 and 0
Specify the position (0/4th/8th byte) to place the ECC in
the control code area.
00: Places the ECC at the 0 to 7th byte of control code
01: Places the ECC at the 4th to 11th byte of control
10: Places the ECC at the 8th to 15th byte of control
11: Setting prohibited
Select Dividing Rates for Flash Clock
Flash Clock Select
QTSEL = 0, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by two and uses it as FCLK.
QTSEL = 0, FCKSEL = 1: Uses a clock (Pφ)
provided from the CPG as FCLK.
QTSEL = 1, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by four and uses it as FCLK.
QTSEL = 1, FCKSEL = 1: Setting prohibited
area
code area
code area