DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 348

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.5.6
SDRAM Interface
(1)
SDRAM Direct Connection
The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,
8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in
read and write command cycles.
The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RD/WR,
DQMUU, DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and
CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted.
SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to
SDRAM can be set to 32 or 16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
the SDRAM operating mode.
Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RD/WR, and specific
address signals. These commands supports:
• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks pre-charge (PALL)
• Specified bank pre-charge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with pre-charge (READA)
• Write (WRIT)
• Write with pre-charge (WRITA)
• Write mode register (MRS, EMRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or
writing is performed for a byte whose corresponding DQMxx is low. For details on the
relationship between DQMxx and the byte to be accessed, see section 9.5.1, Endian/Access Size
and Data Alignment.
Figures 9.14 to 9.16 show examples of the connection of the SDRAM with the LSI.
Rev. 3.00 Sep. 28, 2009 Page 316 of 1650
REJ09B0313-0300