DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 775

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Bit
0
* Only 0 can be written to clear the flag after 1 is read.
Bit Name
DR
Initial
Value
0
R/W
R/(W)* Receive Data Ready
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Indicates that the quantity of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clock
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
[Clearing conditions]
•
•
•
1: Next receive data has not been received
[Setting condition]
•
Note:
remains in SCFRDR after receiving ended normally
DR is cleared to 0 when the chip undergoes a
power-on reset
DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written.
DR is cleared to 0 when all receive data are read
after DMAC is activated by receive FIFO data full
interrupt (RXI).
DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit.*
*
This is equivalent to 1.5 frames with the 8-
bit, 1-stop-bit format. (ETU: Elementary
time unit)
Rev. 3.00 Sep. 28, 2009 Page 743 of 1650
REJ09B0313-0300