DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 181

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1
• 16 levels of interrupt priority can be set
• NMI noise canceler function
• Occurrence of interrupt can be reported externally (IRQOUT pin)
• Register banks
By setting the fifteen interrupt priority registers, the priorities of IRQ interrupts, PINT
interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request
sources.
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
For example, when this LSI has released the bus mastership, this LSI can inform the external
bus master of occurrence of an on-chip peripheral module interrupt and request for the bus
mastership.
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
Features
Section 6 Interrupt Controller (INTC)
Rev. 3.00 Sep. 28, 2009 Page 149 of 1650
Section 6 Interrupt Controller (INTC)
REJ09B0313-0300

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