DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 300

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
• CS6WCR
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 268 of 1650
REJ09B0313-0300
Bit
31 to 21
20
19 to 13
12, 11
R/W:
R/W:
Bit:
Bit:
31
15
R
R
0
0
Bit Name
⎯
BAS
⎯
SW[1:0]
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
0
All 0
00
R/W
28
12
R
0
0
-
SW[1:0]
R/W
27
11
R
0
0
-
R/W
R
R/W
R
R/W
R/W
26
10
R
0
1
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read/write access
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CS6 Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address, CS6
assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
R/W
25
R
0
9
0
-
WR[3:0]
asserts the RD/WR signal during the write access
cycle.
cycle and asserts the RD/WR signal at the write
timing.
R/W
24
R
0
8
1
-
R/W
23
R
0
7
0
-
R/W
WM
22
R
0
6
0
-
21
R
R
0
5
0
-
-
R/W
BAS
20
R
0
4
0
-
19
R
R
0
3
0
-
-
18
R
R
0
2
0
-
-
R/W
17
R
0
1
0
-
HW[1:0]
R/W
16
R
0
0
0
-