DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 695

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a16-bit counter, and can generate interrupts at set intervals.
12.1
• Independent selection of four counter input clocks at two channels
• Selection of DMA transfer request or interrupt request generation on compare match by
• When not in use, the CMT can be stopped by halting its clock supply to reduce power
Figure 12.1 shows a block diagram of CMT.
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
DMAC setting
consumption.
Compare match timer start register
Compare match timer control/status register
Compare match constant register
Compare match counter
Compare match interrupt
Features
Control circuit
Section 12 Compare Match Timer (CMT)
CMI0
Pφ/8
Figure 12.1 Block Diagram of CMT
Pφ/32
Clock selection
Channel 0
Pφ/128
CMT
Module bus
Pφ/512
Control circuit
CMI1
Rev. 3.00 Sep. 28, 2009 Page 663 of 1650
Section 12 Compare Match Timer (CMT)
Pφ/8
Pφ/32
Clock selection
Channel 1
Pφ/128
Peripheral bus
REJ09B0313-0300
Pφ/512
interface
Bus

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