DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 806

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 774 of 1650
REJ09B0313-0300
Figure 15.8 Sample Flowchart for Receiving Serial Data (cont)
Read receive data in SCFRDR
and ORER flag in SCLSR to 0
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
in SCFSR,
BRK = 1?
ER = 1?
DR = 1?
End
Yes
Yes
Yes
Yes
No
No
No
No
• Whether a framing error or parity error
• When a break signal is received,
has occurred in the receive data that
is to be read from the receive FIFO
data register (SCFRDR) can be
ascertained from the FER and PER
bits in the serial status register
(SCFSR).
receive data is not transferred to
SCFRDR while the BRK flag is set.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.

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