DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 990

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-TL1)
(5)
The interrupt mask register is a 16 bit register that protects all corresponding interrupts in the
Interrupt Request Register (IRR) from generating an output signal on the IRQ. An interrupt
request is masked if the corresponding bit position is set to ‘1’. This register can be read or written
at any time. The IMR directly controls the generation of IRQ, but does not prevent the setting of
the corresponding bit in the IRR.
• IMR (Address = H'00A)
Bits 15 to 0: Maskable interrupt sources corresponding to IRR[15:0] respectively. When a bit is
set, the interrupt signal is not generated, although setting the corresponding IRR bit is still
performed.
(6)
The Transmit Error Counter (TEC) and Receive Error Counter (REC) is a 16-bit read/(write)
register that functions as a counter indicating the number of transmit/receive message errors on the
CAN Interface. The count value is stipulated in the CAN protocol specification Refs. [1], [2], [3]
and [4]. When not in (Write Error Counter) test mode this register is read only, and can only be
modified by the CAN Interface. This register can be cleared by a Reset request (MCR0) or
entering to bus off.
In Write Error Counter test mode (i.e. TST[2:0] = 3'b100), it is possible to write to this register.
The same value can only be written to TEC/REC, and the value written into TEC is set to TEC
and REC. When writing to this register, RCAN-TL1 needs to be put into Halt Mode. This feature
is only intended for test purposes.
Rev. 3.00 Sep. 28, 2009 Page 958 of 1650
REJ09B0313-0300
Bit[15:0]: IMRn
0
1
Initial value:
Interrupt Mask Register (IMR)
Transmit Error Counter (TEC) and Receive Error Counter (REC)
R/W:
Bit:
IMR15 IMR14 IMR13 IMR12 IMR11 IMR10
R/W
15
1
R/W
14
1
Description
Corresponding IRR is not masked (IRQ is generated for interrupt conditions)
Corresponding interrupt of IRR is masked (Initial value)
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
IMR9
R/W
9
1
IMR8
R/W
8
1
IMR7
R/W
7
1
IMR6
R/W
6
1
IMR5
R/W
5
1
IMR4
R/W
4
1
IMR3
R/W
3
1
IMR2
R/W
2
1
IMR1
R/W
1
1
IMR0
R/W
0
1