DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 423

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Changing the registers in the BSC while the write buffer is operating may disrupt correct write
access. Therefore, do not change the registers in the BSC immediately after a write access. If this
change becomes necessary, do it after executing a dummy read of the write data.
(3)
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
When the CPU writes data to the internal peripheral registers, the CPU performs the succeeding
instructions without waiting for the completion of writing to registers.
For example, a case is described here in which the system is transferring to the software standby
mode for power savings. To make this transition, the SLEEP instruction must be performed after
setting the STBY bit in the STBCR register to 1. However a dummy read of the STBCR register is
required before executing the SLEEP instruction. If a dummy read is omitted, the CPU executes
the SLEEP instruction before the STBY bit is set to 1, thus the system enters sleep mode not
software standby mode. A dummy read of the STBCR register is indispensable to complete
writing to the STBY bit.
To reflect the change by internal peripheral registers while performing the succeeding instructions,
execute a dummy read of registers to which write instruction is given and then perform the
succeeding instructions.
9.6
9.6.1
When using both the bus arbitration function and the software standby mode, set the bus
arbitration function disable (set the BLOCK bit in CMNCR to 1) before entering the software
standby mode, and set the bus arbitration function enable (set the BLOCK bit in CMNCR to 0)
after cancelling the software standby mode. If the LSI enter the software standby mode in the case
that the BLOCK bit is set to 0, BACK pin outputs low for 1 bus clock (Bφ) cycle after canceling
the software standby mode even though BREQ input is high.
On-Chip Peripheral Module Access
Usage Notes
Note when using both the bus arbitration function and the software standby mode
Rev. 3.00 Sep. 28, 2009 Page 391 of 1650
Section 9 Bus State Controller (BSC)
REJ09B0313-0300