DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 253

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(3)
With the 4-way set associative system, up to four instructions or data with the same entry address
can be registered in the cache. When an entry is registered, LRU shows which of the four ways it
is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU)
algorithm is used to select the way that has been least recently accessed.
Six LRU bits indicate the way to be replaced in case of a cache miss. The relationship between
LRU and way replacement is shown in table 8.1 when the cache lock function (only for operand
cache) is not used (concerning the case where the cache lock function is used, see section 8.2.2,
Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 8.1 is set in the
LRU bits by software, the cache will not function correctly. When modifying the LRU bits by
software, set one of the patterns listed in table 8.1.
The LRU bits are initialized to B'000000 by a power-on reset but not initialized by a manual reset
or in software standby mode.
Table 8.1
LRU (Bits 5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
LRU
LRU and Way Replacement (Cache Lock Function Not Used)
Rev. 3.00 Sep. 28, 2009 Page 221 of 1650
Way to be Replaced
3
2
1
0
REJ09B0313-0300
Section 8 Cache