DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 495

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.3.2
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit
7
6
Bit Name
BFE
Timer Mode Register (TMDR)
Initial value:
Initial
Value
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
BFE
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
R/W
BFB
5
0
operation
R/W
BFA
4
0
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 463 of 1650
R/W
2
0
MD[3:0]
R/W
1
0
R/W
0
0
REJ09B0313-0300

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