DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 870

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 17 I
Rev. 3.00 Sep. 28, 2009 Page 838 of 1650
REJ09B0313-0300
Bit
5
4
3 to 0
Bit Name
MST
TRS
CKS[3:0]
2
C Bus Interface 3 (IIC3)
Initial
Value
0
0
0000
R/W
R/W
R/W
R/W
Description
Master/Slave Select
Transmit/Receive Select
In master mode with the I
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clocked synchronous serial format, MST
is cleared and the mode changes to slave receive
mode.
Operating modes are described below according to
MST and TRS combination. When clocked
synchronous serial format is selected and MST = 1,
clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select
These bits should be set according to the necessary
transfer rate (table 17.3) in master mode.
2
C bus format, when

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