DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 116

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 2 CPU
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
Rev. 3.00 Sep. 28, 2009 Page 84 of 1650
REJ09B0313-0300
Instruction
STC
STC
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA
* In the event of bank overflow, the number of cycles is 19.
GBR,Rn
VBR,Rn
SR,@-Rn
GBR,@-Rn
VBR,@-Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@-Rn
MACL,@-Rn
PR,@-Rn
#imm
practice, the number of instruction execution states in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is the same
as the register used by the next instruction.
Instruction Code
0000nnnn00010010
0000nnnn00100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
GBR → Rn
VBR → Rn
Rn-4 → Rn, SR → (Rn)
Rn-4 → Rn, GBR → (Rn)
Rn-4 → Rn, VBR → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
Rn-4 → Rn, MACH → (Rn)
Rn-4 → Rn, MACL → (Rn)
Rn-4 → Rn, PR → (Rn)
PC/SR → stack area,
(imm × 4 + VBR) → PC
Execu-
tion
Cycles
1
1
2
1
1
1
1
1
1
1
1
5
T Bit
SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

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