DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 364

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 9 Bus State Controller (BSC)
(3)
A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in cache miss.
• 16-byte transfer by DMAC
• 16-byte to 128-byte transfer by LCDC
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus. This access is called the burst read with the burst number 4.
Table 9.17 shows the relationship between the access size and the number of bursts.
Note: For details, see section 24, LCD Controller (LCDC).
Table 9.17 Relationship between Access Size and Number of Bursts
Note:
Rev. 3.00 Sep. 28, 2009 Page 332 of 1650
REJ09B0313-0300
Bus Width
16 bits
32 bits
Burst Read
* 32-, 64-, or 128-byte access occurs when the LCDC is used. For details, see section
24, LCD Controller (LCDC).
Access Size
8 bits
16 bits
32 bits
16 bits
32 bytes*
64 bytes*
128 bytes*
8 bits
16 bits
32 bits
16 bits
32 bytes*
64 bytes*
128 bytes*
Number of Bursts
1
1
2
8
16
32
64
1
1
1
4
8
16
32

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