DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 194

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 6 Interrupt Controller (INTC)
6.3.8
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 162 of 1650
REJ09B0313-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
Bank Control Register (IBCR)
R/W
Bit Name
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E15
15
0
R/W
E14
14
0
R/W
E13
13
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
E12
12
0
R/W
E11
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
E10
10
0
Description
Enable
These bits enable or disable use of register banks for
interrupt priority levels 15 to 1. However, use of register
banks is always disabled for the user break interrupts.
0: Use of register banks is disabled
1: Use of register banks is enabled
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W
E9
9
0
R/W
E8
8
0
R/W
E7
7
0
R/W
E6
6
0
R/W
E5
5
0
R/W
E4
4
0
R/W
E3
3
0
R/W
E2
2
0
R/W
E1
1
0
R
0
0
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