DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 237

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.3.5
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupt requests, (2) including or excluding of the data bus value, (3) internal CPU bus or
internal DMA bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or
write, and (7) operand size as the break conditions.
Initial value:
Bit
15, 14
13
12
11, 10
R/W:
Bit:
Break Bus Cycle Register (BBR)
Bit Name
⎯
UBID
DBE
⎯
15
R
0
-
14
R
0
-
UBID
R/W
13
0
Initial
Value
All 0
0
All 0
0
R/W
DBE
12
0
11
R
0
-
R/W
R
R/W
R/W
R
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
1: Data bus condition is included in break conditions
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
9
0
CP[1:0]
conditions
R/W
8
0
R/W
7
0
CD[1:0]
Rev. 3.00 Sep. 28, 2009 Page 205 of 1650
R/W
6
0
Section 7 User Break Controller (UBC)
R/W
5
0
ID[1:0]
R/W
4
0
R/W
3
0
RW[1:0]
REJ09B0313-0300
R/W
2
0
R/W
1
0
SZ[1:0]
R/W
0
0