DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 981

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TSEG2:
The RCAN-TL1 Bit Rate Calculation is:
Where BRP is given by the register value and TSEG1 and TSEG2 are derived values from TSG1
and TSG2 register values. The ‘+1’ in the above formula is for the Sync-Seg which duration is 1
time quanta.
BCR Setting Constraints
These constraints allow the setting range shown in the table below for TSEG1 and TSEG2 in the
Bit Configuration Register. The number in the table shows possible setting of SJW. "No" shows
that there is no allowed combination of TSEG1 and TSEG2.
Bit Rate =
TSEG1min > TSEG2 ≥ SJWmax
8 < TSEG1 + TSEG2 + 1 < 25 time quanta (TSEG1 + TSEG2 + 1 = 7 is not allowed)
f
TSEG2 > 2
CLK
= Peripheral Clock
TSG2 + 1
2 × (BRP + 1) × (TSEG1 + TSEG2 + 1)
f
clk
(SJW = 1 to 4)
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 949 of 1650
REJ09B0313-0300

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