DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 859

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note: Hatching boxes represent SSU internal operations.
[1]
[3]
[4]
No
Read received data in SSRDR
Read receive data in SSRDR
Clear the ORER bit in SSSR
RDRF automatically cleared
Overrun error processing
Consecutive data reception?
End reception
End reception
Initial setting
Read SSSR
ORER = 1?
RDRF = 1?
RE = 0
Start
Figure 16.16 Flowchart Example of Data Reception
Yes
Yes
No
(Clock Synchronous Communication Mode)
Yes
No
[2]
[1]
[2], [4] Receive error processing:
[3]
Section 16 Synchronous Serial Communication Unit (SSU)
Initial setting:
Specify the receive data format.
When a receive error occurs, execute the designated error
processing after reading the ORER bit in SSSR. After that,
clear the ORER bit to 0. While the ORER bit is set to 1,
reception is not resumed.
To complete reception:
To complete reception, read receive data after clearing the
RE bit to 0. When reading SSRDR without clearing the RE
bit, reception is resumed.
Rev. 3.00 Sep. 28, 2009 Page 827 of 1650
REJ09B0313-0300

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