DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1664

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev. 3.00 Sep. 28, 2009 Page 1632 of 1650
REJ09B0313-0300
Item
28.1.1 Power-Down
Modes
Table 28.1 States of
Power-Down Modes
28.2.9 System Control
Register 3 (SYSCR3)
28.2.11 Deep Standby
Control Register 2
(DSCTR2)
28.2.13 Deep Standby
Cancel Source Flag
Register (DSFR)
Page
1399
1413
1417
1420
Revision (See Manual for Details)
Notes amended
Notes: 2. RTC operates when the START bit in the RCR2
Description amended
SYSCR3 is an 8-bit readable/writable register that performs
the software reset control for the SSI0 to SSI3
the operation of the crystal resonator for audio. Only byte
access is valid.
Table amended
Description amended
DSCTR2 is an 8-bit readable/writable register that controls
the state of the external bus control pins and specifies the
startup method when deep standby mode is canceled. Only
byte access is valid.
Table amended
Figure amended
Initial value:
Bit
Bit
7
7
R/W:
Bit:
Bit Name
AXTALE
Bit Name
CS0KEEPE
R/(W)
KEEP
15
IO
0
register is set to 1. For details, see section 14,
Realtime Clock (RTC). When deep standby mode
is canceled by a power-on reset, the running state
cannot be retained. Make the initial setting for the
realtime clock again.
14
R
0
-
13
R
0
-
Initial
Value
0
Initial
Value
0
12
R
0
-
11
R/W
R/W
R/W
R/W
R
0
-
10
R
0
-
MRESF NMIF
R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W)
Description
AUDIO_X1 Clock Control
Controls the function of AUDIO_X1 pin.
0: Runs the on-chip crystal oscillator/enables the
1: Halts the on-chip crystal oscillator/disables the
Description
Retention of External Bus Control Pin State
0: The state of the external bus control pins is not
1: The state of the external bus control pins is
9
0
external clock input.
external clock input.
retained when deep standby mode is canceled.
retained when deep standby mode is canceled.
8
0
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
7
0
6
0
5
0
4
0
3
0
2
0
and
1
0
0
0