DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 949

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Important: Although core of RCAN-TL1 is designed based on a 32-bit bus system, the whole
RCAN-TL1 including MPI for the CPU has 16-bit bus interface to CPU. In that case, LongWord
(32-bit) access must be implemented as 2 consecutive word (16-bit) accesses. In this manual,
LongWord access means the two consecutive accesses.
• Micro Processor Interface (MPI)
• Mailbox
• Mailbox Control
The MPI allows communication between the Renesas CPU and the RCAN-TL1’s
registers/mailboxes to control the memory interface. It also contains the Wakeup Control logic
that detects the CAN bus activities and notifies the MPI and the other parts of RCAN-TL1 so
that the RCAN-TL1 can automatically exit the Sleep mode.
It contains registers such as MCR, IRR, GSR and IMR.
The Mailboxes consists of RAM configured as message buffers and registers. There are 32
Mailboxes, and each mailbox has the following information.
<RAM>
⎯ CAN message control (identifier, rtr, ide, etc)
⎯ CAN message data (for CAN Data frames)
⎯ Local Acceptance Filter Mask for reception
<Registers>
⎯ CAN message control (dlc)
⎯ Time Stamp for message reception/transmission
⎯ 3-bit wide Mailbox Configuration, Disable Automatic Re-Transmission bit, Auto-
⎯ Tx-Trigger Time
The Mailbox Control handles the following functions.
⎯ For received messages, compare the IDs and generate appropriate RAM addresses/data to
⎯ To transmit event-triggered messages, run the internal arbitration to pick the correct
⎯ Arbitrates Mailbox accesses between the CPU and the Mailbox Control.
⎯ Contains registers such as TXPR, TXCR, TXACK, ABACK, RXPR, RFPR, UMSR and
Transmission for Remote Request bit, New Message Control bit
store messages from the CAN Interface into the Mailbox and set/clear appropriate registers
accordingly.
priority message, and load the message from the Mailbox into the Tx-buffer of the CAN
Interface and set/clear appropriate registers accordingly. In the case of time-triggered
transmission, compare match of Tx-Trigger time invoke loading the messages.
MBIMR.
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 917 of 1650
REJ09B0313-0300