DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 769

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
7
Bit Name
ER
Initial
Value
0
R/W
R/(W)* Receive Error
Section 15 Serial Communication Interface with FIFO (SCIF)
Description
Indicates the occurrence of a framing error, or of a
parity error when receiving data that includes parity.*
0: Receiving is in progress or has ended normally
[Clearing conditions]
•
•
1: A framing error or parity error has occurred.
[Setting conditions]
•
•
Notes: 1. Clearing the RE bit to 0 in SCSCR does
ER is cleared to 0 a power-on reset
ER is cleared to 0 when the chip is when 0 is
written after 1 is read from ER
ER is set to 1 when the stop bit is 0 after checking
whether or not the last stop bit of the received
data is 1 at the end of one data receive
operation*
ER is set to 1 when the total number of 1s in the
receive data plus parity bit does not match the
even/odd parity specified by the O/E bit in SCSMR
2. In two stop bits mode, only the first stop
not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the receive data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCFRDR includes a receive error
can be detected by the FER and PER bits
in SCFSR.
bit is checked; the second stop bit is not
checked.
2
Rev. 3.00 Sep. 28, 2009 Page 737 of 1650
REJ09B0313-0300
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