DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 1651

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Item
4.3 Clock Operating
Modes
Table 4.3 Relationship
between Clock Operating
Mode and Frequency
Range
4.4.1 Frequency Control
Register (FRQCR)
Table 4.5 CKOEN[1:0]
Settings
4.5.3 Note on Using Pll
Oscillation Circuit
4.6 Usage of the Clock
Pins
4.7 Oscillation
Stabilizing Time
4.8 Notes on Board
Design
5.2.4 Manual Reset
Page
112
114
115
⎯
118, 119 Newly added
120
121
132
Revision (See Manual for Details)
Caution amended
Caution: Do not use this LSI for frequency settings other than
Table amended
Table added
Deleted
Newly added
Newly added
Description amended
When manual reset exception processing is started by the
WDT, the CPU operates in the same way as when a manual
reset was caused by the MRES pin.
(3) Note in Manual Reset
When a manual reset is generated, the bus cycle is retained,
but if a manual reset occurs while the bus is released or
during DMAC burst transfer, manual reset exception handling
will be deferred until the CPU acquires the bus. …
Bit
13, 12
Bit Name
CKOEN[1:0]
those in table 4.3.
Initial
Value
00
R/W
R/W
Rev. 3.00 Sep. 28, 2009 Page 1619 of 1650
Description
Clock Output Enable
Specifies the CKIO pin outputs clock signals, or is set
to a fixed level or high impedance (Hi-Z) during
normal operation mode, release of bus mastership,
standby mode, or cancellation of standby mode.
If these bits are set to 01, the CKIO pin is fixed at low
during standby mode or cancellation of standby
mode. Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock during cancellation
of standby mode can be prevented. In clock operating
mode 2, the CKIO pin functions as an input
regardless of the value of these bits. In deep standby
mode, the normal state is retained.
The settings are shown under the CKOEN[1:0] bits in
table 4.5.
REJ09B0313-0300