DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 474

no-image

DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.17 shows the TEND output timing.
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for
an 8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.
When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS
signal for data alignment as shown in figure 10.18. Figures 10.13 to 10.17 show the cases where
DACK and TEND are not divided in the DMA transfer.
Rev. 3.00 Sep. 28, 2009 Page 442 of 1650
REJ09B0313-0300
CKIO
Bus cycle
DREQ
DACK
TEND
Figure 10.17 Example of DMA Transfer End Signal Timing
DMAC
(Cycle Steal Mode Level Detection)
CPU
End of DMA transfer
DMAC
CPU
CPU

Related parts for DS72030W200FPV