DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 897

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.7
The logic levels at the SCL and SDA pins are routed through noise filters before being latched
internally. Figure 17.17 shows a block diagram of the noise filter circuit.
The noise filter consists of three cascaded latches and a match detector. The SCL (or SDA) input
signal is sampled on the peripheral clock. When NF2CYC is set to 0, this signal is not passed
forward to the next circuit unless the outputs of both latches agree. When NF2CYC is set to 1, this
signal is not passed forward to the next circuit unless the outputs of three latches agree. If they do
not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
Noise Filter
D
Sampling clock
Peripheral clock
Latch
C
cycle
Figure 17.17 Block Diagram of Noise Filter
Q
D
Latch
C
Q
D
Latch
C
NF2CYC
Q
Rev. 3.00 Sep. 28, 2009 Page 865 of 1650
Section 17 I
detector
detector
Match
Match
2
C Bus Interface 3 (IIC3)
1
0
REJ09B0313-0300
Internal
SCL or SDA
signal