DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 420

• Manufacturer Part Number: DS72030W200FPV
• Description: MPU, 32BIT, SH7203, ROMLESS, 240QFP
• Manufacturer: Renesas Electronics America
• Series: SH7200r

Specifications of DS72030W200FPV

• Core Size: 32bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 240
• Supply Voltage Range: 1.1V To 1.3V
• Operating Temperature Range: -20°C To +85°C
• Svhc: No SVHC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
the high-impedance state at subsequent rising edges of CKIO. Bus request signals are sampled at
the falling edge of CKIO. Note that CKE, RASU, RASL, CASU, and CASL can be continued to
be driven at the previous value even in the bus-released state by setting the HIZCNT bit in
CMNCR.
The sequence for reclaiming the bus mastership from an external device is described below. 1.5
cycles after the negation of BREQ is detected at the falling edge of CKIO, the bus control signals
are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The
fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the
rising edge of the CKIO where address and data signals are driven. Figure 9.55 shows the bus
arbitration timing.
When it is necessary to refresh SDRAM while releasing the bus mastership, the bus mastership
should be returned using the REFOUT signal. For details on the selection of REFOUT, see section
25, Pin Function Controller (PFC). The REFOUT signal is kept asserting at low level until the bus
mastership is acquired. The BREQ signal is negated by asserting the REFOUT signal and the bus
mastership is returned from the external device. If the bus mastership is not returned for a
refreshing period or longer, the contents of SDRAM cannot be guaranteed because a refreshing
cannot be executed.
While releasing the bus mastership, the SLEEP instruction (to enter sleep mode, deep standby
mode, or software standby mode), as well as a manual reset, cannot be executed until the LSI
obtains the bus mastership.
The BREQ input signal is ignored in software standby mode or deep standby mode and the BACK
output signal is placed in the high impedance state. If the bus mastership request is required in this
state, the bus mastership must be released by pulling down the BACK pin to enter software
standby mode or deep standby mode.
The bus mastership release (BREQ signal for high level negation) after the bus mastership request
(BREQ signal for low level assertion) must be performed after the bus usage permission (BACK
signal for low level assertion). If the BREQ signal is negated before the BACK signal is asserted,
only one cycle of the BACK signal is asserted depending on the timing of the BREQ signal to be
negated and this may cause a bus contention between the external device and the LSI.
Rev. 3.00 Sep. 28, 2009 Page 388 of 1650
REJ09B0313-0300