DS72030W200FPV Renesas Electronics America, DS72030W200FPV Datasheet - Page 368

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DS72030W200FPV

Manufacturer Part Number
DS72030W200FPV
Description
MPU, 32BIT, SH7203, ROMLESS, 240QFP
Manufacturer
Renesas Electronics America
Series
SH7200r
Datasheet

Specifications of DS72030W200FPV

Core Size
32bit
Program Memory Size
32KB
Cpu Speed
200MHz
Digital Ic Case Style
QFP
No. Of Pins
240
Supply Voltage Range
1.1V To 1.3V
Operating Temperature Range
-20°C To +85°C
Svhc
No SVHC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Section 9 Bus State Controller (BSC)
(4)
A read access ends in one cycle when data exists in a cache-disabled space and the data bus width
is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst
length 1, only the required data is output. A read access that ends in one cycle is called single read.
Figure 9.19 shows the single read basic timing.
Rev. 3.00 Sep. 28, 2009 Page 336 of 1650
REJ09B0313-0300
Single Read
Figure 9.19 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)
RASL, RASU
CASL, CASU
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
CSn
BS
1
2
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Tr
Tc1
Td1
Tde
(Tap)

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